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Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided...
This study presents a new test method for Through Silicon Via (TSV) in 3D stacked ICs, in which a Delay-Locked Loop (DLL) is utilized to detect TSV defects. As compared to TSV test methods using free running ring oscillators, the proposed method presents a much better performance against Process, supply Voltage and Temperature (PVT) variations due to the inherent feedback of DLL systems. In the proposed...
3D IC using Through Silicon Via (TSV) is a promising technology for next generation of integrated circuits. Manufacturing TSV defects like voids and pinholes have to be detected at the test phase to ensure fault free ICs. In this paper a contactless probe utilizing capacitive coupling is presented. The proposed method eliminates the impact of direct probing on TSV and supports the high-density and...
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