The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents the design of a low gain-error pseudo rail-to-rail indirect current feedback instrumentation amplifier (In-Amp). In order to reduce the gain error introduced by the input common mode voltage variations, MOS transconductors regulated by specially designed folded-cascoded amplifier are used. Simulated gain error is only about 0.2% with input common mode voltage ranging from half...
A high linear double-gate (DG) MOSFET application to RF mixer is proposed based on derivative superposition method which was successfully used in Bulk CMOS region. By independently biasing front and back gate voltage of DG MOSFET, one DG MOSFET device is reviewed as two parallel devices. In this way, we realize the derivative superposition method application in the DG MOSFET linearity analysis and...
A novel nano-scale lateral double-gate tunneling field effect transistor (LDG-TFET) is proposed in this paper and its performance is shown through two dimensional device numerical simulations. The study result demonstrates that this new tunneling transistor allows for the steeper sub-threshold swings, e.g. below 60 mV/Dec, the super low supply voltage, e.g. operable at VDD <0.2V and the high ratio...
ULTRA-SOI is a new generation of the channel-potential-based non-charge-sheet model for the dynamic depletion (DD) Silicon-On-Insulator (SOI) MOSFET, developed by TSRC group in EECS department of Peking University with many year efforts. The model is formulated with a fully physical derivation from the Poisson's equation to solve the potential along the vertical direction of the silicon film. The...
This paper describes a web-based platform for nanoscale non-classical device modeling and circuit simulation, especially for non-classical CMOS device compact modeling and circuit performance prediction. This platform is based on program libraries, including model code files. We use SPICE as circuit simulation framework, and the Verilog-A as model design language. Based on the user input deck content,...
This paper describes a method to integrate non-planar multi-gate CMOS devices in the third dimension. The technology is based on highly scalable multi-gate MOSFET structures which are promising for nano-scale integration. The extension to have active devices placed the third dimension allow significant reduction in the interconnect loading. We have demonstrated the potential of such technology though...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.