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Background: Domino logic is widely used in modern digital systems because of easy implementation with less number of transistors and high speed. The pre-charge and evaluation phases of the domino logic, leads to enormous transitions at the output. This switching of the output is undesirable as it leads to more dynamic power dissipation. Methods: This achieved by the using the structures such as True...
Background/Objectives: Domino logic designs are widely used owing to its high speed and less area. However, the on chip variation of the design becomes more severe on scaling down the technology nodes. Methods/Statistical analysis: This paper details the design of variation tolerant domino logic with novel keeper architecture which comprises of a stacked grounded keeper with a body-bias generator...
The paper presents the design of 8-bit adder structures based on the Carry Look Ahead (CLA) and Carry Skip Adder (CSKA) architectures by employing the High Speed Clock Delayed (HSCD) domino logic. The paper presents the adder circuits constructed using dual threshold voltage devices and comparison have been made for the circuits while operating with normal Vth transistors to analyze the use of dual...
The constant delay (CD) logic makes high speed operation of the dynamic circuits possible. In the CD logic, the timing block plays a vital role as it helps in reduction of the evaluation time, by defining a small window width. This paper proposes a modified timing block which yields minimized area even while accomplishing the function. Use of the CD logic across cascaded stages employing the proposed...
Floating point numbers are used in various applications such as medical imaging, radar, telecommunications Etc. This paper deals with the comparison of various arithmetic modules and the implementation of optimized floating point ALU. Here pipelined architecture is used in order to increase the performance and the design is achieved to increase the operating frequency by 1.62 times. The logic is designed...
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