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With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage consumption has become an important concern in low power and high performance applications for nano-scale CMOS processes. This paper presents a MTCMOS (multi-threshold CMOS) power-gating scheme for single-phase adiabatic circuits, which minimizes leakage dissipations during sleep mode. The 8-bit full adder based...
Tracking constitutes a major challenge in Ultra-Wideband (UWB)communications due to dense multipath environment and low power consumption. Most of the existing studies on tracking fall within low rate Impulse Radio UWB (IR-UWB) scope, with the assumption that Inter-Frame Interference (IFI) or Inter-Symbol Interference (ISI) is absent. In this paper, we settle on high rate Direct-Sequence UWB (DS-UWB)...
This paper presents an adiabatic tree multiplier based on modified Booth algorithm, which operates in a single-phase power-clock. All circuits are realized using improved CAL (clocked adiabatic logic) circuits with TSMC 0.18 mum CMOS process. The proposed single-phase adiabatic booth encoder attains energy savings of 82% at 50 MHz and 70% at 300 MHz, compared with its CMOS counterpart. The single-phase...
This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating...
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