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In this work we propose the use of Diversity Combining Techniques with frequency despreading as an efficient way to improve the BER performance of the IEEE802.15.4g OFDM mode, as well as, to reduce the SNR required for the Physical Layer Header (PHR) detection. As alternatives, we propose the use of Maximal Ratio Combining (MRC), Subcarrier Selection (SC) or a combination of SC and MRC (SMRC). An...
This work proposes a transceiver architecture for the OFDM PHY of IEEE802.15.4g standard targeting Smart Metering Utility Networks. It also details the main components implemented for preliminary hardware prototyping. The OFDM transceiver is part of a project that is under development and aims to implement in ASIC the three PHYs defined by the IEEE802.15.4g standard, i.e. MR-FSK, MR-OQPSK and MR-OFDM...
This demo presents the implementation of an MR-OFDM baseband modem, in FPGA, compliant with the recently released IEEE802.15.4g standard. Such standard is devoted to Smart Metering Utility Networks. The modem was designed using VHDL and prototyped on Altera's device 5CGXFCC5C6F27C7N. The prototype supports all MR-OFDM configurations and its maximum FPGA speed is 65.16 MHz. The modem was evaluated...
This paper presents the architecture of a pilot-based Fine Frequency Estimator (FFE) based on a modified version of the Luise & Reggiannini (L&R) algorithm. The proposed architecture uses a serial correlator implementation to reduce the hardware complexity. The estimator was implemented targeting a digital receiver for the DVB-S2 standard, and with minor changes it can also support DVB-S2X...
This paper presents the implementation of a FEC decoding subsystem for a DVB-S2 compliant receiver. The FEC decoder is composed by three blocks: De-interleaver, LDPC and BCH decoders, and its main goal is correcting the bits that were corrupted by the channel during transmission. The DVB-S2 standard defines several coding schemes and interleaving methods for protecting the data, and all the configurations...
This paper presents a proposal of an Adaptive Equalizer based on DFE, and its implementation in FPGA, to make DVB-S2 transmission reliable under ISI (specially for wideband transmissions) and to make possible the mobile reception over satellite links for QPSK modulation. The Equalizer also presents the potential to reduce the nonlinear distortion effects, which are typically found in the satellite...
Design and implementation of signal processing and synchronization algorithms for digital receivers are challenging tasks, especially concerning the verification phase that must cover as many functional tests as possible. This paper discloses the entire internal architecture of the receive chain of the ETSI DVB-S2 digital satellite communication standard and the methodology used for implementing it...
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