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This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided...
This paper proposes a dependable dual-port SRAM with 9T/18T bitcell structure. The proposed SRAM has two operating modes: a 9T normal mode and an 18T dependable mode. The 9T bitcell has an outside single-ended bitline as a dedicated read port along with a pair of conventional differential inside bitlines. Therefore, the 18T bitcell has two differential pairs of the outside bitlines and inside bitlines...
We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system...
We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system...
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, "quality of a bit (QoB)" for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells for one-bit information (i.e. 14T/bit)...
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