Search results for: John McAllister

Items from 1 to 20 out of 32 results

article

Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA

Yun Wu, John McAllister

IEEE Transactions on Parallel and Distributed Systems > 2018 > 29 > 1 > 43 - 55

Field Programmable Gate Array (FPGA) boast abundant resources with which to realise high-performance accelerators for computationally demanding operations. Highly efficient accelerators may be automatically derived from Signal Flow Graph (SFG) models by using architectural synthesis techniques, but in practical design scenarios, these currently operate under two important limitations - they cannot...

article

Bounded Selective Spanning With Extended Fast Enumeration for MIMO-OFDM Systems Detection

Yun Wu, John McAllister

IEEE Transactions on Circuits and Systems I: Regular Papers > 2017 > 64 > 9 > 2556 - 2568

Sphere decoders allow receivers in multiple-input multiple-output (MIMO) communications systems to detect QAM symbols with quasi-optimal accuracy and low complexity compared with the ideal maximum likelihood detector. However, their high complexity relative to simple linear detectors means that the latter are still usually adopted, despite their lower detection performance. Configurable sphere decoders,...

chapter

Multicore distributed dictionary learning: A microarray gene expression biclustering case study

Stephen Laide, John McAllister

2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP) > 1168 - 1172

2017 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The increasing pervasion and scale of machine learning technologies is posing fundamental challenges for their realisation. In the main, current algorithms are centralised, with a large number of processing agents, distributed across parallel processing resources, accessing a single, very large data object. This creates bottlenecks as a result of limited memory access rates. Distributed learning has...

article

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Matthew Milford, John McAllister

IEEE Transactions on Signal Processing > 2016 > 64 > 16 > 4152 - 4165

Field-programmable gate arrays are ideal hosts to custom accelerators for signal, image, and data processing but demand manual register transfer level design if high performance and low cost are desired. High-level synthesis reduces this design burden but requires manual design of complex on-chip and off-chip memory architectures, a major limitation in applications such as video processing. This paper...

article

Streaming Elements for FPGA Signal and Image Processing Accelerators

Peng Wang, John McAllister

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2016 > 24 > 6 > 2262 - 2274

Field-programmable gate array (FPGA) devices boast abundant resources with which custom accelerator components for signal, image, and data processing may be realized; however, realizing high-performance, low-cost accelerators currently demands manual register transfer level design. Software-programmable soft processors have been proposed as a way to reduce this design burden, but they are unable to...

chapter

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

Xuezheng Chu, John McAllister, Roger Woods

Lecture Notes in Computer Science > Reconfigurable Computing: Architectures, Tools and Applications > Reconfigurable Processors > 133-144

The most promising way to maintain reliable data transfer across the rapidly fluctuating channels used by next generation multiple-input multiple-output communications schemes is to exploit run-time variable modulation and antenna configurations. This demands that the baseband signal processing architectures employed in the communications terminals must provide low cost and high performance with run-time...

chapter

Memory-Centric Hardware Synthesis from Dataflow Models

Scott Fischaber, John McAllister, Roger Woods

Lecture Notes in Computer Science > Embedded Computer Systems: Architectures, Modeling, and Simulation > Special Session: System Level Design for Heterogeneous Systems > 197-206

Generation of hardware architectures directly from dataflow representations is increasingly being considered as research moves toward system level design methodologies. Creation of networks of IP cores to implement actor functionality is a common approach to the problem, but often the memory sub-systems produced using these techniques are inefficiently utilised. This paper explores some of the issues...

chapter

Introduction to System Level Design for Heterogeneous Systems

John McAllister

Lecture Notes in Computer Science > Embedded Computer Systems: Architectures, Modeling, and Simulation > Special Session: System Level Design for Heterogeneous Systems > 146-146

For the current generation of heterogeneous multi-core embedded processor, Systemon-Chip and FPGA platforms, implementation and optimisation of Digital Signal and Image Processing applications is an exceptionally challenging task, with the widely accepted viewpoint being that moving towards high abstraction (system) level design principles is the only feasible option to increasing the productivity...

book

Reconfigurable Computing: Architectures, Tools and Applications

Andreas Koch, Ram Krishnamurthy, John McAllister, Roger Woods, more

Lecture Notes in Computer Science

This book constitutes the refereed proceedings of the 7th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2011, held in Belfast, UK, in March 2011. The 40 revised papers presented, consisting of 24 full papers, 14 poster papers, and the abstracts of 2 plenary talks, were carefully reviewed and selected from 88 submissions. The topics covered are reconfigurable...

chapter

FPGA-based DSP

John McAllister

Handbook of Signal Processing Systems > Architectures Managing Editor: Jarmo Takala > 363-392

Field Programmable Gate Array (FPGA) offers an excellent host embedded device for DSP systems when real-time performance beyond that which multiprocessor platforms can achieve is required, but volumes are too small to justify the costs of developing a custom chip. This niche role is due to the ability of FPGA to host custom computing architectures, tailored to the application. Modern FPGAs play host...

article

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies

John McAllister, Maire O’Neill, Maxime Pelcat

Journal of Signal Processing Systems > 2016 > 84 > 3 > 293-294

chapter

Evolutionary requirements for next-generation dataflow-based FPGA system design

John McAllister

2009 17th European Signal Processing Conference > 2688 - 2692

2009 17th European Signal Processing Conference

The use of dataflow digital signal processing system modelling and synthesis techniques has been a fruitful research theme for many years and has yielded many powerful rapid system synthesis and optimisation capabilities. However, recent years have seen the spectrum of languages and techniques splinter in an application specific manner, resulting in an ad-hoc design process which is increasingly dependent...

article

Guest Editorial: Special Issue on Embedded Computer Systems: Architectures, Modeling and Simulation

John McAllister, David Guevorkian, Hartwig Jeschke, Mihai Sima

International Journal of Parallel Programming > 2015 > 43 > 1 > 1-2

chapter

FPGA-based Tabu search for detection in large-scale MIMO systems

Yun Wu, John McAllister

2014 IEEE Workshop on Signal Processing Systems (SiPS) > 1 - 6

2014 IEEE Workshop on Signal Processing Systems (SiPS)

The increasing scale of Multiple-Input Multiple-Output (MIMO) topologies employed in forthcoming wireless communications standards presents a substantial implementation challenge to designers of embedded baseband signal processing architectures for MIMO transceivers. Specifically the increased scale of such systems has a substantial impact on the perfor-mance/cost balance of detection algorithms for...

chapter

High performance real-time Pre-Processing for Fixed-Complexity Sphere Decoder

Yun Wu, John McAllister, Peng Wang

2013 IEEE Global Conference on Signal and Information Processing > 1250 - 1253

2013 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

Pre-processing (PP) of received symbol vector and channel matrices is an essential pre-requisite operation for Sphere Decoder (SD)-based detection of Multiple-Input Multiple-Output (MIMO) wireless systems. PP is a highly complex operation, but relative to the total SD workload it represents a relatively small fraction of the overall computational cost of detecting an OFDM MIMO frame in standards such...

chapter

Software defined FFT architecture for IEEE 802.11ac

Peng Wang, John McAllister, Yun Wu

2013 IEEE Global Conference on Signal and Information Processing > 1246 - 1249

2013 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

The upcoming IEEE 802.11ac standard boosts the throughput of previous IEEE 802.11n by adding wider 80 MHz and 160 MHz channels with up to 8 antennas (versus 40 MHz channel and 4 antennas in 802.11n). This necessitates new 1–8 stream 256/512-point Fast Fourier Transform (FFT) / inverse FFT (IFFT) processing with 80/160 MSample/s throughput. Although there are abundant related work, they all fail to...

chapter

Soft-core stream processor for sliding window applications

Peng Wang, John McAllister

SiPS 2013 Proceedings > 213 - 218

2013 IEEE Workshop on Signal Processing Systems (SiPS)

Software-programmable ‘soft’ processors have shown tremendous potential for efficient realisation of high performance signal processing operations on Field Programmable Gate Array (FPGA), whilst lowering the design burden by avoiding the need to design fine-grained custom circuit archi-tectures. However, the complex data access patterns, high memory bandwidth and computational requirements of sliding...

article

Decreasing Operating Room Contamination of Surfaces and Air with Pulsed Xenon Ultraviolet Disinfection

Ana Fridman, Lou Ann Bruno-Murtha, Rebecca Osgood, John McAllister

AJIC: American Journal of Infection Control > 2013 > 41 > 6 Supplement > S36

chapter

Soft-core stream processing on FPGA: An FFT case study

Peng Wang, John McAllister, Yun Wu

2013 IEEE International Conference on Acoustics, Speech and Signal Processing > 2756 - 2760

ICASSP 2013 - 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

The increasing design complexity associated with modern Field Programmable Gate Array (FPGA) has prompted the emergence of 'soft'-programmable processors which attempt to replace at least part of the custom circuit design problem with a problem of programming parallel processors. Despite substantial advances in this technology, its performance and resource efficiency for computationally complex operations...

chapter

Bounded selective spanning with extended fast enumeration for MIMO-OFDM systems detection

Yun Wu, John McAllister

21st European Signal Processing Conference (EUSIPCO 2013) > 1 - 5

2013 21st European Signal Processing Conference (EUSIPCO)

Selective Spanning Fast Enumeration (SSFE) is a promising detection approach for Multiple-Input Multiple-Output (MIMO) systems which allows detection performance to be traded off against computational complexity depending on the communications environment. However, SSFE suffers from two drawbacks: its symbol enumeration strategy cannot properly span modulation schemes of 16 QAM or greater, leading...

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FIELD PROGRAMMABLE GATE ARRAYS (11)
MIMO (9)
FPGA (6)
DECODING (5)
MOTION ESTIMATION (5)
REAL-TIME SYSTEMS (5)
THROUGHPUT (5)
IEEE 802.11N STANDARD (4)
PROGRAM PROCESSORS (4)
SPHERE DECODER (4)
COMPLEXITY THEORY (3)
COMPUTER ARCHITECTURE (3)
DATAFLOW (3)
DETECTORS (3)
FIELD PROGRAMMABLE GATE ARRAY (FPGA) (3)
HARDWARE SYNTHESIS (3)
MULTICORE PROCESSING (3)
PROCESSOR (3)
REAL TIME SYSTEMS (3)
TABLE LOOKUP (3)
BANDWIDTH (2)
FAST FOURIER TRANSFORM (FFT) (2)
KERNEL (2)
MEMORY HIERARCHY (2)
MEMORY MANAGEMENT (2)
MIMO COMMUNICATION (2)
MULTICORE (2)
MULTIPLE-INPUT MULTIPLE-OUTPUT (MIMO) (2)
OFDM (2)
PIPELINES (2)
RANDOM ACCESS MEMORY (2)
REGISTERS (2)
VECTORS (2)
16-QAM (1)
802.11AC (1)
802.11N (1)
ABSTRACTS (1)
ANTENNA (1)
ANTENNA ARRAYS (1)
ANTENNAS (1)
ARCHITECTURAL SYNTHESIS (1)
BER (1)
BICLUSTERING (1)
BIT ERROR RATE (1)
BLAST (1)
BLOCK DATA ADDRESSING (1)
COMPUTATIONAL COMPLEXITY (1)
CUTTING EDGE MIMO STANDARDS (1)
DATA REUSE (1)
DATAFLOW GRAPH (1)
DEDICATED CIRCUIT-BASED ARCHITECTURES (1)
DESIGN AUTOMATION (1)
DICTIONARIES (1)
DIGITAL SIGNAL PROCESSING (1)
DIGITAL SIGNAL PROCESSING CHIPS (1)
DISTRIBUTED (1)
DISTRIBUTED DATABASES (1)
DYNAMIC RANGE (1)
EQUATIONS (1)
ERROR STATISTICS (1)
FAST-FOURIER TRANSFORM (FFT) (1)
FFT/IFFT (1)
FIELD-PROGRAMMABLE GATE ARRAY (FPGA) (1)
FIXED-COMPLEXITY SPHERE DECODER (FSD) (1)
FLEXIBLE MODULATION SCHEMES (1)
FLOATING-POINT IMPLEMENTATION (1)
FPGA DSP CHIP MULTIPROCESSORS (1)
FPGA HOST PROGRAMMABLE DATAPATHS (1)
FPGA SOFTCORE PROCESSORS (1)
FPGA STREAMING ELEMENT PROCESSOR (1)
FSD (1)
FSD DETECTOR (1)
GENE EXPRESSION (1)
HARDWARE (1)
HARDWARE SOLUTIONS (1)
HETEROGENEOUS SISD-SIMD-MIMD ARCHITECTURES (1)
INSTRUCTION SETS (1)
INTERLEAVE (1)
INTERLEAVING (1)
LOOP ACCELERATOR (1)
MACHINE LEARNING (1)
MANUALS (1)
MATHEMATICAL MODEL (1)
MATRIX DECOMPOSITION (1)
MATRIX INVERSION (1)
MATRIX MULTIPLICATION (1)
MATRIX MULTIPLICATION (MM) (1)
MEMORY ARCHITECTURE (1)
MICROARRAY GENE EXPRESSION (1)
MIMO RECEIVER (1)
MIMO-OFDM FIXED-COMPLEXITY SPHERE DECODER (1)
MODIFIED SQUARED GIVENS ROTATION (1)
MODULATION (1)
MULTI-INPUT MULTI-OUTPUT (MIMO) (1)
MULTIPLE-INPUT MULTIPLE-OUTPUT (MIMO) DETECTION (1)
MULTIPLE-INPUT MULTIPLE-OUTPUT COMMUNICATION SYSTEM (1)
MULTIPROCESSING SYSTEMS (1)
MULTIPROCESSOR INTERCONNECTION (1)
NEXT GENERATION MULTIPLE-INPUT MULTIPLE-OUTPUT COMMUNICATION SYSTEMS (1)
OFDM MODULATION (1)
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INFONA - science communication portal

Search results for: John McAllister

Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA

Bounded Selective Spanning With Extended Fast Enumeration for MIMO-OFDM Systems Detection

Multicore distributed dictionary learning: A microarray gene expression biclustering case study

Constructive Synthesis of Memory-Intensive Accelerators for FPGA From Nested Loop Kernels

Streaming Elements for FPGA Signal and Image Processing Accelerators

A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection

Memory-Centric Hardware Synthesis from Dataflow Models

Introduction to System Level Design for Heterogeneous Systems

Reconfigurable Computing: Architectures, Tools and Applications

FPGA-based DSP

Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies

Evolutionary requirements for next-generation dataflow-based FPGA system design

Guest Editorial: Special Issue on Embedded Computer Systems: Architectures, Modeling and Simulation

FPGA-based Tabu search for detection in large-scale MIMO systems

High performance real-time Pre-Processing for Fixed-Complexity Sphere Decoder

Software defined FFT architecture for IEEE 802.11ac

Soft-core stream processor for sliding window applications

Decreasing Operating Room Contamination of Surfaces and Air with Pulsed Xenon Ultraviolet Disinfection

Soft-core stream processing on FPGA: An FFT case study

Bounded selective spanning with extended fast enumeration for MIMO-OFDM systems detection

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