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Hardware errors are becoming more prominent with reducing feature sizes, however tolerating them exclusively in hardware is expensive. Researchers have explored software-based techniques for building error resilient applications for hardware faults. However, software based error resilience techniques need configurable and accurate fault injection techniques to evaluate their effectiveness. In this...
Previous studies have suggested using drowsy caches to reduce leakage power in caches. Such studies often move an entire cache line in and out of the drowsy mode to reduce leakage power while maintaining performance. In this work we extend previous work and introduce Application Specific Low Leakage Cache (ASL) as an alternative power-aware data cache for embedded processors. ASL builds on the observation...
Voltage scaling can reduce power dissipation significantly. SRAM cells (which are traditionally implemented using six-transistor cells) can limit voltage scaling due to stability concerns. Eight-transistor (8T) cells were proposed to enhance cell stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. Previous work has proposed...
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