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This paper presents compressive image sensor techniques based on sparse measurement matrices. Existing compressive sensing (CS) CMOS image sensors use dense random measurement matrices, which face the challenges of excessive hardware overhead and large signal swing requirement. The sparse measurement matrices proposed in this paper dramatically simplify the circuit implementation and relax the signal...
This paper presents low power circuit design for voltage regulator and resistor to digital converter that are used in a RFID-like sensing circuit for measuring the resistance of a sol-gel sensor. The regulator circuit has simple circuit structure and consumes zero DC current (except the current drained by its load). The resistor to digital converter consists of a cascoded current mirror, a reference...
This paper presents a novel design of low power charge redistribution successive approximation analog to digital converter (CR-SAR ADC). During its conversion, the voltage swing of the capacitor array is reduced to half of the voltage reference without decreasing the ADC dynamic range. The reduced voltage swing results in a significant reduction of ADC power consumption. Also, the proposed design...
This paper presents a novel design of address pointer for FIFO memory circuits. Advantages of the proposed design include: reduced capacitive load on the pointer clock path, the use of a true single-phase clock, and double- edge-triggering clock scheme. The circuit has low power consumption, is immune to circuit racing conditions and suitable for high-speed operations. Techniques to implement clock...
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