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The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. The integration of dedicated hardware to enhance the performance of the run-time management system is gaining an increasing importance. But the design of a run-time manager for many-core generally suffers from exhaustive evaluation...
Many-core systems provide abundant computing power for parallel applications. The run-time manager of an embedded system has to efficiently exploit the available resources while guaranteeing a high responsiveness. We propose a dedicated hardware infrastructure to improve the scalability and responsiveness of a run-time task manager. The hardware enhancements constitute a hierarchy of global and local...
Enhancing an electrical NoC with a reconfigurable nano-photonic interconnect architecture contributes to mitigate the bandwidth bottleneck typically found in modern systems. The management of such photonic channels, however, complicates the control of the network and deteriorates its predictability. For the autonomous management of the photonic links with full predictability, this work proposes a...
Herewith you will find the Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2015) held in Bremen (Germany), from June 29th to July 1st 2015. ReCoSoC, during the past decade, has grown and established itself as an international reference event for research in the areas of reconfigurable and communication-centric systems-on-chip. Its informal...
Optical network-on-chips (oNoCs) are a promising candidate to replace electrical NoCs in many-core systems. Nanophotonic components provide high bandwidth and short transmission delay but they are very sensitive to the temperature. Temperature gradients are typically found on many-core systems. The precise reconstruction of the core's temperature and the prediction of its evolution are an inevitable...
The increasing number of processing elements on embedded many-cores gives novel challenges for the chip design. Dedicated hardware has become an important feature to support the applied operating system and to improve the overall system efficiency. Since evaluation of novel architectures requires time expensive simulations or prototyping, transaction-level analysis gives an appropriate tool for early...
The increasing requirements for bandwidth and quality-of-service motivate the use of parallel interconnect architectures with several degrees of reconfiguration. This paper presents an IP, called Distributed Channel Management (DCM), to extend existing packet-switched NoCs with a reconfigurable point-to-point network seamlessly, i.e., without the need for any modification on the routers. The configuration...
The trend for multicore processor architectures indicates an ongoing increase in computing cores per chip. The resulting challenges demand for a revision of the applicability of existing hardware operating systems. We propose a scalable best-effort task scheduler implemented in hardware, which services a homogeneous multiprocessor architecture. The hardware scheduler realizes a master/slave system...
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