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UTBB FDSOI technology is a faster, cooler and simpler technology addressing the performance/energy consumption trade-off. In this paper we present the main front-end-of-the-line knobs to scale down this promising technology to the 10nm node.
For the first time we report extremely thin SOI (ETSOI) CMOS with 22 nm gate length (LG) and sub-100 nm contacted gate pitch for system-on-chip (SoC) applications. Multi-Vt transistors are demonstrated with competitive drive currents (NFET/PFET) of 1150/1050 µA/µm at Ioff = 100 nA/µm for high performance (HP) and 920/880 µA/µm at Ioff = 1 nA/µm for low power (LP), respectively, at VDD = 1 V. High...
This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art gate-all-around devices. 25 nm times 20 nm times 10 nm (LxWxTSi) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented...
This work highlights the new bulk+ technology using high-K dielectric, single metal gate and fully depleted SON (silicon on nothing) channel for sub-45 nm low cost applications. Thin silicon channel (down to Tsi= 8 nm) and thin BOX (Tbox = 15 to 25 nm) are obtained using the SON process (Jurczak, 1999). Transistor performance (Wdesign/Lgate= 90 nm/40 nm) at Vdd = 1.1 V and Ioff < 2 nA/ mum is as...
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