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A development of the VeSTIC technology is reported. The manufacturing of the test structures with different types of transistors is described. The electrical 1-V characteristics of the MOS and junction field effect transistors and of the bipolar junction transistors produced in VeSTIC technology were measured. Basic parameters of the test devices were extracted using the simple device compact models...
A process for manufacturing of the p-type piezoresistor-based monolithic strain sensors is described. The process variants regarding resistor doping techniques and the sensor design are discussed. The offset measurement results are reported. For a detailed characterization of the piezoresistive sensors by the electrical measurements a dedicated test structure has been proposed. Van der Pauw and Kelvin...
A method for fabrication of VeSFETs, three-dimensional fin-type MOS transistors is presented. The VeSTIC process was developed and experimentally implemented in ITE. The test devics were manufactured, and their electrical characteristics were measured. Methods for extraction of a set of the VeSFET physical parameters are proposed based on the device compact model. The flat-band voltage, mobility and...
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