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This study presents a 3-GHz DLL-based clock generator with stuck locking protection. In this paper, a proposed duty cycle corrector solves the problem of the sensitivity to half transparent (HT) architecture and the stuck locking error in the DLL simultaneously. Based on the frequency-multiplied technique, the multiphase DLL architecture synthesizes a 3-GHz output clock. The post-layout simulation...
A high-speed current mode sense amplifier for Spin Torque Transfer Magnetic Random Access Memory (STT MRAM) is proposed. The sense amplifier is designed in a 0.18 μm CMOS technology, and 1.8 V supply voltage. The resistance values of high state is 2132 Ω, low state is 1215 Ω, and reference state is 1512 Ω, respectively. The proposed sense amplifier decreases the dropping rate of input bias. In particular,...
In phase-locked loop (PLL), the loop parameters such as loop bandwidth, phase margin and damping factor must be adjusted to minimize jitter and to guarantee stability. According to the restrictions of the PLL, this paper employs formula derives to find the relationship between the loop parameters. Therefore, the PLL uses time-to-digital converter (TDC) and programmable current mirror (PCM) to adjust...
A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD. Fine locking is achieved by the phase shifter for the sake of fast locking. Measure results show that the maximum clock skew of the proposed...
An arbitrary duty cycle synchronous mirror delay (SMD) circuit is proposed in this paper. The conventional SMD can be locked in 2 clock cycles, but it just can accept only the narrow pulse clock signal, which will greatly restrict the application of the circuits. The modified TSPC DFF is used in the proposed SMD circuit to detect clock edge. Therefore, the proposed SMD circuit not only can be locked...
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