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This paper, proposes a new architecture to reduce the silicon area of the Cartesian feedback (CFB) used to linearize a power amplifier in WCDMA communication standard. The first stage of the previous version consists of two CORDIC structures in vector mode for the phase computation following by a subtractor. Here, we propose to merge these two CORDIC structures to obtain directly the phase difference...
In this paper, a smart adaptive RF power amplifier linearization technique is presented. We invest a Mixed-Signal Cartesian Feedback Loop design to train an embedded Random Access Memory in order to overcome digital-stage latency and bandwidth limitation. The new design consists of a traditional analog stage including filters, I/Q modulator, feedback I/Q demodulator and an improved digital stage which...
In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve...
Intensive research in the networking domain addresses content- and context-aware features for the Future Internet. Thus, being able to manipulate data flows and to adapt those to given constraints with a minimum resource involvement is a hot topic. On top of this topic, video manipulation is the challenge to undertake in order to optimize resource-consuming processes. However, developing heterogeneous...
The expansion of the market for embedded systems has motivated academic research to offer solutions to the problems of congestion and connectivity. Indeed, the implementation of the embedded processor on FPGA helps saving space and provides a better interaction between the program and hardware acceleration. Furthermore, the addition of an Operating System (OS) allows to abstract the hardware and to...
Many communications embedded systems implement decimation filters. In particular, base-band stage in multistandard receivers is composed of cascade of decimation filters performing channel selection. The number of used filter and the kind of these filters can have a significant impact on the computation complexity and power consumption of multistandard receivers. In This work we present FIR filters'...
In this paper, a new adaptive power amplifier (PA) linearization technique is presented. The idea is to consider a classic WCDMA Zero-Intermediate Frequency (Zero-IF) transmitter with a modified Cartesian feedback (CFB) loop. The new transmitter architecture consists of an analog stage including forward I/Q modulator and feedback I/Q demodulator and a digital stage adjusting the phase rotation around...
The Interest in synthesis of custom Digital Signal Processors (DSP) using automated design flow like High Level Synthesis greatly increased in the last years. This phenomenon is due to the growing processing complexity and the time to market constraint. Dedicated processor component design is a complex process, for which tools must optimize the datapath and it s controller. In this paper, we propose...
The idea behind this work is to extract from a large number of FIR filter syntheses several curves that estimate the area and power consumption. The aim is to help filter designer to make the right choice regarding decimation factor versus area and power consumption. The performed experiences show that for a given filter order, the choice of the decimation factor has a deep impact on the area and...
Upgradeability and interoperability are main concerns of Software Defined Radio (SDR). But in the case of military applications, security is also a relevant aspect of SDR. The Secure Software Communication Architecture (SSCA) is a standardized solution to secure SDR. This architecture needs a cryptographic processor for security purposes. However, currently available SSCA compliant ASIC-based cryptoprocessors...
High-level synthesis (HLS) currently seems to be an interesting process to reduce the design time substantially. HLS tools actually map algorithms to architectures. While such tools were developed targeting ASIC technologies, HLS currently draws wide interest for FPGA designers. However with most of HLS techniques, traditional resource sharing models are very inaccurate for FPGAs: for example, multiplexers...
This work presents a low-power multistandard decimation and channel selection filter architecture. The filter is suitable after an over-sampling sigma-delta converter and performs decimation in two stages. The first stage is a modified structure of the cascade of integrators-combs (CIC) filter and allows reducing sampling rate downto only the double of the Nyquist frequency. The second stage composed...
This paper presents an efficient design of a decimation filter for a continuous-time (CT) complex lowpass SigmaDelta modulator in multi-standard receiver. The proposed architecture fulfills the requirements of three standards: Wi-max, UMTS and GSM. The optimization of the proposed decimation structure leads to two implementation architectures which are optimized in different ways: area (in terms of...
Modern communication technologies need faster analog- to-digital converters (ADC). To significantly increase the sampling rate of an ADC, time-interleaved ADC (TIADC) is an efficient solution. A M-channels TIADC is composed of M ADCs which operate at interleaved sampling times. Due to the manufacturing process, the main drawback of a TIADC system is that the MADCs are not exactly the same. This means...
This work deals with low-power design of a decimation filter used in a wireless multi-standard receiver. We propose a solution that reduces the dynamic power consumption by reducing the filtering activity. This solution uses the clock-gating technique on parallel filters combined with appropriate clock distribution. We optimize the arithmetic operators to save area with the power consumption and increase...
To significantly increase the sampling rate of an ADC, time-interleaved ADC (TIADC) is an efficient solution. Due to the manufacturing process, the main drawback of a TIADC system is that the M ADCs, which compose this end, are not exactly the same. This means that offset, gain and time mismatch errors are introduced. These errors cause distortions in the output sampled signal and introduce unwanted...
In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose or digital signal processor though hardware components can cope with throughput and power constraints. In this paper we propose a methodology to implement multiple configuration (or mode) and multi-constraint systems into a single...
Intellectual property protection (IPP) is one of the most important challenges for digital design development. Intelectual properties (IP) and their reuse are usual today, but the use of IP design is raising design security issues. Watermarking is one of the efficient methods to detect an unauthorized use of an IP. A lot of interesting works have been proposed, but only a few of them combine watermarking...
To increase the sampling rate of Analog to Digital Converters (ADC), Time-Interleaved ADC (TIADC) is an efficient solution. However, offset mismatch, gain mismatch, and timing errors between time-interleaved channels limit the TIADC performances. This setting presents a new adaptive method for gain and offset mismatch error compensation. The technique proposed is based on adaptive filtering process...
This study was initiated in the frame of the 2-stage, 32-demultiplexed input digital filter of the large correlator system of the ALMA (Atacama Large Millimeter Array) interferometer project. The main goal of this work was to reduce the power consumption of the implemented architecture in large FPGAs by optimizing the amount of logic elements. A modified structure of the CIC (cascaded integrator comb)...
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