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We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive...
The goal of this work is to study parameters related to the analog performance of tunnel field effect transistors (TFETs). The obtained results have been analyzed in terms of temperature variation (ranging from 25°C to 150°C) and source composition (Sh-xGex and 100% Si). The first part is focused on characteristic curves of the drain current as a function of gate voltage and drain voltage. Next step...
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