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This paper presents the measured results and characterisation of a 1.2 V CMOS low phase noise quadrature output phase locked loop (PLL) with an on-chip regulated DC-DC converter. In particular, it exhibits a phase noise response of less than -115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 38%. The automatic amplitude control loop in the VCO gives the facility to trade-off...
A complete analysis of the spur characteristics of edge-combining delay-locked loop (DLL)-based frequency multipliers is presented in this brief. The novelty of this analysis is the fact that it can be used to estimate the effect of both the in-lock error and the delay-stage mismatch on the spurious level of the frequency multiplier with low computational complexity. In addition, a way to reduce the...
This paper presents a comparative study on the difference in the performance of a differential negative resistance LC-VCO when CMOS and bipolar transistors are used in its implementation. Both the noise magnitude of these transistors and the noise up-conversion mechanisms are used to identify the best selection of devices in designing a low phase noise LC-VCO. This study was performed using the IHP...
This paper presents the design of a low phase noise 1.6 GHz CMOS buffered quadrature output VCO with automatic amplitude control. It is operated with a supply voltage of 1.2 V and dissipates a current of less than 10 mA. It is capable of delivering quadrature locked signals with almost constant amplitude in the range from 1.22 GHz to 1.95 GHz with a phase noise response of less than -115 dBc at an...
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