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Authors describe firstly obtained necessary and sufficient conditions for detection of a logic component output fault in the combination logic structure controlled on the basis of Berger code. It is demonstrated that for the solution of the given task not only Berger code property of identifying any unidirectional errors in data vectors, but also the property of any asymmetric errors detection may...
Authors offer the way of formation of self-checking concurrent error detection systems of combinational circuits based on Boolean complement method with “1-out-of-5”-code. This code's checker needs five code words for full test and has low technical realization complexity. This allows organization of concurrent error detection system with reduced structural redundancy compared with duplication method...
The article covers the issues of the synthesis of self-checking discrete systems. The authors introduced the method of building modified codes with summation of weighted transitions between the bits taking neighboring positions in data vectors. The new codes with summation possess the same number of check bits as classical Berger codes, but detect more errors in data vectors. Modified codes with summation...
Characteristics of codes with summation of unit data bits are analyzed, the latter are often applied in technical diagnostics of discrete systems' problems. The contributors of the article suggest a fundamentally new method of summation code modification, based on decomposition of data vectors' digits, the formation of new vectors, weight estimation and writing down the obtained figures in corresponding...
A detailed analysis of error controlled divisible codes' building techniques was carried out, aimed at error detection in data vectors, which relate to summation codes' class. Summation codes classification was suggested, covering the whole diversity of modification methods of the existing classical and modular summation codes. New methods of summation codes modification were specified making it possible...
The article proposes a new approach for organization of concurrent error detection (CED) systems of combinational logic circuits. This approach implies the implementation of combinational circuit layout analysis, as well as consideration of the features of separable codes with higher error detection performance for errors with low multiplicities. CED system supposed to be built based on division the...
The authors of this article proposed a new universal algorithm of building modified sum codes, that generalizes known methods of code formation, as well as allows to build new sum codes, implementation of which might be useful for technical diagnostics problems solving. The algorithm is based on segregation of bits into a data vector and its division onto two subsets (possibly intersecting), on the...
The article provides a method of building the sum code, that detects any errors of double multiplicity in data vectors. This characteristic can be effectively used for organizing the concurrent error detection (CED) systems of combinational logic circuits. The paper explains new sum code characteristics, and also states the properties of this code for error detection in data vectors. Also there is...
The article provides a structure of combinational circuit concurrent error detection (CED) systems, that implements the principle of Boolean complement of logic functions, on the base of constant-weight code «2-out-of-4» (2/4-code). It also shows the benefits of using the 2/4-code in comparison with code «1-out-of-4» (1/4-code) for organization of CED systems of combinational circuits.
The article provides the method of concurrent error detection (CED) system organisation, based on the constant-weight 1/3-code, with outputs of testing logic circuit combined into groups by 3 outputs. The authors provide the calculation formulas of check functions of complements, that allow not only to form the set of testing combinations for «1-out-of-3»-code (1/3-code) checker, but also to form...
The article provides a method of formation of the sum code with minimum total number of undetectable errors in data vectors. The idea of building this code is based on the principle of weighing of data vector bits, obtaining the weight of data vector and following modifications of its value. New code has the same number of bits in check vectors, as classic Berger code, however, it also has high detection...
In this article the features of sum codes for error detection in data vectors are discussed, that is of interest at the time of concurrent error detection (CED) systems organization. The article describes a classic sum code (Berger code), as well as weighted data bits sum code. It includes the method of code formation, that is optimum with regard to error detection in data vectors. This code has the...
In this article the study of characteristics of modular sum codes for error detection in concurrent error detection (CED) systems is presented. The article provides the classification of sum codes with arbitrary modulus values. It also gives the definition of common patterns in detection ability of all modular sum codes. Determined characteristics of modular sum codes are supported by the results...
The authors of this article provides a formation method for the sum code with improved characteristics for error detection in data vectors, comparing to the similar performances of classic Berger codes. Error detection efficiency improvement is achieved due to modification of weighted transition sum code according to specified rules. New modified sum code has a minimum total number of undetectable...
In this paper authors consider the problem of concurrent error detection (CED) system of combinational circuit with unidirectionally independent outputs design using modulo codes with the summation. Considering of error detection features of modulo codes with the summation allows designing CED systems with reduced complexity comparing with the ones based on the classic Berger code. Authors determine...
In this article the characteristics of on-bit and one weighted bit sum codes for distortions detection in concurrent error detection systems (CED systems) are described. Conditions under which the weight-based sum code will have all key characteristics of classic Berger code are established. Established features of weight-based sum codes in practice allow to choose the best coding option while organizing...
In this paper we consider binary codes with summation used at designing test systems of combinational logical circuits. We offer new codes, determine their properties and compare these codes with each other.
Features of Berger and Hamming codes application in testable logical devices synthesis are described in this paper. Some new error-detection properties of these codes are determined; this is actual for concurrent error detection (CED) systems. Codes' properties are compared and Hamming code CED system check equipment synthesis method is described on the example of code with 4 informational bits checker...
In this paper authors adduce results of the research in the theory of synthesis of concurrent error detection (CED) circuits based on use of codes with summation. New codes with summation are obtained and their properties of errors among data bits detection are determined. The complete classification of codes with summation is adduced.
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