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On-chip global interconnects are speed and power bottleneck in state-of-the-art chips. Pre-emphasis technique is an efficient way to improve the performance of the global communication. This paper first performs delay analysis of a global wire to work with a pre-emphasis circuit in time domain. Based on the analysis, a new pre-emphasis circuit design is proposed. Simulation results show that the pre-emphasis...
High speed and low power transceivers start to be used for global interconnection in state-of-the-art System-on-Chips (SoCs). In traditional transceivers, the bandwidth is largely dependent on the clock rate. This paper presents a clock-less transceiver for global interconnect. The asynchronous transceiver makes the data rate only depend on the link delay and can be conveniently used with low swing...
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