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Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated...
Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect...
Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. Typical mitigation techniques induce large overheads in terms of resource usage and power consumption. We propose a new approach achieving efficient trade-offs between robustness and overheads, applied to the internal architecture of commercial AT40K devices.
The robustness of a chip designed for security-related applications depends on its capability to globally resist to various types of attacks. This paper deals with protections against non invasive or semi invasive attacks. The two main categories are attacks based on power consumption (either by monitoring the current, e.g. DPA, or by monitoring the electromagnetic emissions, i.e. EMA) and attacks...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
Differential Fault Analysis (DFA) is one of the most powerful techniques to attack cryptosystems. Several countermeasures have been proposed, which are based either on information or temporal redundancy. In this work, we propose a novel approach based on a Double-Data-Rate (DDR) computation template. A few sample architectures have been implemented: they are compared to other existing architectures...
Fault injections can easily break a cryptosystem: hence, many dedicated error detection schemes have been proposed, relying on various forms of redundancy (e.g., temporal redundancy). In this paper, we analyze the error detection coverage of two AES implementations, based on the double-data-rate computation template, with emulated faults of several durations.
Several techniques have been proposed for encryption blocks in order to provide protection against faults. These techniques usually exploit some form of redundancy, e.g. by means of error detection codes. However, protection schemes that offer an acceptable error detection rate are in general expensive, while temporal redundancy heavily affects the throughput. In this paper, we propose a new design...
When designing circuits for security-related applications, the robustness depends on its capability to globally resist to various types of attacks, based either on the observation of the device (e.g. differential power analysis) or its perturbation (e.g. injecting faults with a laser). To deal with perturbations, two strategies are developed: detecting the attack or maintaining the proper functioning...
The robustness of a chip designed for security-related applications depends on its capability to globally resist to various types of attacks. Fault-based attacks are classically countered by information redundancy (data encoding). This paper shows that codes with similar detection efficiency can have very different characteristics with respect to other types of attacks based on power consumption analysis
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