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A multi-task-oriented security processing architecture is presented in this paper. This architecture contains a host microprocessor and multiple security processors (SP). The SP could integrate dedicated Crypto-Engines, which provides functional extensibility. And the performance scalability and multi-task parallelism could be enhanced by increasing the number of SPs on system bus. It's demonstrated...
This paper presents a power efficient reconfigurable correlator for DTMB channel estimation. In this design, a novel architecture based on fast Walsh transform is adopted to perform cyclic correlation. By sharing memory and reusing calculation unit, the proposed reconfigurable architecture supports correlation of PN sequence with code length of 256 and 512 without any increment in hardware cost. Based...
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