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This paper proposes a hardware-efficient time-domain scheme to digitally compensate the I/Q imbalance and LO feedthrough (LOFT) of a sub-GHz wideband transmitter for the IEEE 802.11af WLAN. A simple envelope detector is the only analog part. The parameters are updated by Least-Mean-Square and estimated efficiently in time domain by using COordinate Rotation DIgital Computer (CORDIC), saving the training...
A continuous-time/discrete-time (CT/DT) hybrid channel-selection filter (CSF) with a built-in pole-controllable dc-offset canceller (DOC) for WLAN receivers is proposed. Optimized in a 90-nm CMOS process, a 4th-order CT/DT Hourglass architecture plus one frequency-extended real pole approximates the shape of a generic 5th-order pure CT (active-RC) Butterworth structure, while achieving a stable cutoff...
Two circuit techniques adopted in the design of an embedded programmable-gain amplifier (PGA) for very low-voltage (LV) wireless local-area network systems are presented. A switched-current-resistor (SCR) technique minimizes the bandwidth variation and the transient in gain tuning by stabilizing, concurrently, the PGA's feedback factor and quiescent-operating point. Another technique, inside-opamp...
The proliferation of multiple WLANs and the continuous scaling of CMOS have created the need for low-voltage multistandard WLAN receivers. Instead of approaching a complicated SoC, a 3D-stack SiP appears as a promising alternative to meet those requirements in conjunction with the obvious goals of low power and low cost. This paper, focused on the SiP implementation of a WLAN receiver, presents the...
Presented is a low-voltage low-power analog-baseband IC featuring a two-step channel-selection architecture for a flexible-IF reception of 802.11a/b/g. In circuits, it integrates innovatively series-switching mixers for a precise I/Q demodulation; an inside-opamp dc-offset cancellation for area savings and switchability, a switched-current-resistor programmable-gain amplifier for a transient-free...
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