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We present an energy efficient QRS detector for real-time ECG signal processing implemented in ASIC. An adaptive thresholding scheme based on forward search interval (FSI) algorithm together with simple preprocessing is proposed to accurately detect QRS peaks. The Verilog HDL codes with improved hardware utilization efficiency are validated using FPGA, achieving 99.59% sensitivity (Se) and 99.63%...
This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB1dB) at ≥40MHz offset and 6.8dB blocker NF at...
This brief presents an ultra-low-power low-noise chopped capacitively coupled instrumentation amplifier (CCIA) that is suitable for neural recording applications. An active high-pass filter is embedded in the ripple reduction loop (RRL) to suppress the residual noise and relax the capacitor size. Multiple chopping is employed to further reduce the residual output ripple due to the RRL offsets. A dc...
This paper describes an electromagnetic interference (EMI)-resisting Bandgap voltage reference. Its basic topology is a Kuijk Bandgap with a PMOS pass device and an active load, improved to generate a low voltage output (441.3mV) via substituting BJT by MOSFET while preserving a low temperature coefficient (TC). A double differential pair and a power-supply independent bias jointly enhance the EMI...
This paper reports the design and optimization of a standard cell library in 0.18µm CMOS, together with the analysis on voltage scaling and transistor sizing for ultra-low power biomedical applications. By simulating with a 8-bit 4-tap FIR filter at 0.6V clocked 100kHz, the design achieves 18.6× and 1.55× lower power consumption comparing to a commercial standard cell library working at nominal voltage...
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