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This paper presents a low-power 9-bit compiled successive-approximation register (SAR) analog-to-digital converter (ADC) for Bluetooth low energy receivers. The ADC is compiled from a SPICE netlist, a technology rule file, and an object definition file into a design rule check and layout versus schematic clean layout and schematic in 28-nm FDSOI. The compiled SAR ADC reduces the design time necessary...
A Class AB time gain compensation (TGC) circuit and a switched current analog beam former are designed for an ultrasound low power front-end receiver. The TGC also acts as a voltage to current converter with a peak to peak single-ended input voltage range of 1.8V and a ratio of single sided input current swing to bias current is close to 10. The total power consumption of the fully differential TGC...
An Analog RAM architecture for beamforming based on switched current circuits is presented. The proposed architecture allows the sharing of the same bias current for different memory cells, hence results in a large amount of power saving. The beamformer consists of total 16 channels and in each channel a delay line with depth of 16 has been implemented. The input frequency is 10MHz and a sampling...
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