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Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory...
This paper presents a high parallel macro block level layered LDPC decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates and code lengths. LDPC codes defined in WiMAX standard with 6 code rates and 19 code lengths are chosen as the demonstration of this architecture. Based on the proposed dedicated matrix reordering strategy, this decoder costs...
Based on the particular structure of parity check matrix (PCM) of LDPC codes in WiMAX and WiFi wireless communication standards, a new early stopping criterion (SC) is proposed to save the unnecessary decoding iterations. By using the proposed SC, decoding process will be stopped if all the information bits in a code word are corrected even if there are still some errors in the redundant (parity)...
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