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A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A...
A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal...
A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS)...
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