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Soft error is one of the major threats for resilient computing. Unlike SRAM soft error, which can be effectively protected by ECC, Flip-Flop soft error protection can be costly. We observe that flip-flops/latches can have asymmetric soft error rates when storing different logic values. This asymmetry can be used in conjunction with the different signal probabilities of registers in a design. In this...
Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an embedded processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application...
This paper investigates the use of combined read and write assist techniques to reduce the minimum operating voltage (VMIN) of the 6T SRAM bit-cell. While write failures initially limit VMIN, applying write assist introduces row and column half-select failures. Thus, read and write assist must be combined to allow scaling VMIN down to near/sub threshold voltages. We find that combining negative bitline...
We live in an interconnected world. Computing power once reserved for server rooms now resides in our pockets. Tablets now outsell PCs. As marked as these changes have been, we are now entering a new era of vastly greater connectivity, where people interact with the world around them in entirely new ways. The Internet of Things is in its infancy, so predictions of precisely what it will become are...
The conventional guard band design approach increases the SRAM Wordline (WL) pulse duration to operate successfully in all the process, voltage and temperature (PVT) corners. This can significantly increase the dynamic energy. This work presents a digital circuit that is able to track and control the WL pulse duration of the SRAM memory across PVT variations, to minimize the dynamic energy while maintaining...
Device variability in modern processes has become a major concern in SRAM design leading to degradation of both performance and yield. Variation induced offset in the sense amplifiers requires a larger bitline differential, which slows down SRAM access times. In this paper, we propose a post fabrication technique that takes advantage of the typically detrimental bias temperature instability (BTI)...
As process technology scales, SRAM robustness is compromised. In addition, lowering the supply voltage to reduce power consumption further reduces the read and write margins. To maintain robustness, a new bitcell topology, 8-T bitcell, has been proposed and read where write operation can be separately optimized. However, it can aggravate the half select disturb when write word-line boosting is applied...
This paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness...
Read and write assist techniques are now commonly used to lower the minimum operating voltage (Vmin) of an SRAM. In this paper, we review the efficacy of four leading write-assist (WA) techniques and their behavior at lower supply voltages in commercial SRAMs from 65nm, 45nm and 32nm low power technology nodes. In particular, the word-line boosting and negative bit-line WA techniques seem most promising...
A wide variety of memory topics addressing design trends at advanced technology nodes. Variation tolerant and low power approaches are discussed as well as their application to SRAM, DRAM, Non-volatile memories and DDR5 interfaces.
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