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Differences in power supply noise (PSN) between functional and structural delay testing can lead to differences in chip operating frequencies of 30% or more. High delay correlation between structural and functional test requires the paths under test to experience the worst-case realistic PSN. We present a PSN control method for pseudo functional test that combines random flipping and background patterns...
Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having power supply noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip,...
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