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The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault...
This paper describes a model-based functional test generation method for hardware designs. The main principles are as follows. Two models are extracted from an HDL description: a functional model, which represents the design under scrutiny, and a coverage model, which represents a set of testing goals. Each goal is specified in the negative form to force a model checker to find a counterexample —...
In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of...
The increasing complexity of hardware designs makes functional verification a challenge. The key issue of the state-of-the-art verification approaches is to obtain a “good” model for automated test generation or formal property checking. In this paper, we describe techniques for deriving EFSM-based models from HDL descriptions and briefly discuss applications of such models for verification. The distinctive...
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