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We report and analyze the dependence of complex gates delay with the sensitization vector and its variation—that gets up to 40% in 65-nm CMOS technologies—and include its effect in the path delay estimation—that can be in the order of 16%. The gate delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable...
We present a Single Event Transient (SET) propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the output noise characteristics given the input noise waveform for each gate, and is applied to a 65-nm technology...
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