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Due to continued miniaturization, semiconductor-based components used in high-performance digital microelectronics are becoming increasingly sensitive to cosmic rays and solar particle events. In the context of high-altitude flight control systems based on fly-by-wire techniques, this may produce sensor noise or affect actuator control signals. Although the consequences so far have been simply reductions...
Whereas the use of FPGAs in aerospace applications is increasing, concerns about its sensitivity to radiations more particularly the single event upsets (SEU) in SRAM-based FPGA is enhanced as well. To ensure hardness assurance, radiation sensitivity should be estimated at different stages of the system development cycle. In this paper, we present a multi-abstraction level signature generation based...
In this paper a methodology for creating a high-level faulty models library for simulating low-level fault injection is proposed. The concept of faulty behavior Signature is first proposed in this work. This paper demonstrates how faulty behavior Signatures allow building high level models, for example using Simulink, that reflect with high fidelity the faulty behavior of a combinational circuit represented...
This paper presents a fault tolerant flight control system. The Extended Multiple Model Adaptive Estimation EMMAE method is used to design the Fault Detection and Diagnosis FDD process. This process is able to detect, isolate and identify in real time faults that occurs in aircraft actuator. Based on information given by FDD process, a Sliding Mode Controller (SMC) is designed to compensate effects...
This paper presents a novel object based communication strategy to interconnect design tools and system components operating at various abstraction levels to produce a consistent and coherent system. Interconnects are generated from interface models. This platform can be used to prototype, validate, simulate and/or test the complex systems interactions before all the components are built and integrated...
Functional verification is a major hurdle in todaypsilas design flow. Current technologies are not meeting the challenges imposed by design complexity. Dark corners detection is still the simulation bottleneck in the verification process. While functional verification remains not sufficiently mature, test techniques are improved and completely automated, accordingly complex circuits can be tested...
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