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This paper proposes a system-on-chip design to perform run-time reconfiguration using soft-core processor. The reconfigurable module consists of a set of Processing Elements (PEs) that are fully connected to each other through a crossbar network. Run-time reconfiguration is achieved by dynamically selecting the desired number of PEs based on the input data set through soft-core processor. This dynamic...
This paper proposes an injection locked four stage differential ring voltage controlled oscillator (VCO) in which in-phase and quadrature phase of the reference signal is injected after the first stage, for both frequency multiplication and division. The free running frequency of 4-stage differential VCO is 485MHz. Frequency Multiplication is carried out by injecting a reference frequency of 1.25GHz...
Modelling a PLL based 40MHz integer-N frequency synthesizer to identify and eliminate the reference spurs. The macro-model has a gain margin of 6.64dB and a phase margin of 43.1°, ensuring the stability of the closed loop system with a settling time of 3.85μsec. A notch-type comb filter was modelled to eliminate the periodically occurring reference spurs observed at 20MHz and 60MHz.
A 4-channel Time-Interleaved analog to digital convertor with 12-bits of resolution and sampling rate of 4 giga samples per second for 60GHz applications is designed using MATLAB SIMULINK macro blocks. The interleaving channels of Time-Interleaving analog to digital convertor(ADC) architecture, has a 4 stage Pipelined ADC with a 3-bit flash ADC followed by a 3-bit digital to analog convertor(DAC)...
This paper presents a hardware implementation solution to a real time stereo matching problem using system of associative relations (SOAR) computational model. SOAR makes use of pair-wise pixel interactions captured as direction of derivatives to determine the underlying structure of associations within an analysis token. SOAR also offers a similarity measure to assess similarity of two such structures...
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