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Given a synthesized digital integrated circuit comprising interconnected library cells, and assuming arbitrary (continuous) sizes for the cells, experimentally, we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). An accurate table-lookup delay model was developed from the precharacterized industrial...
We introduce the concept of utilizing two cell libraries, one for synthesis and another for physical design. The physical library consists of only 9 functions, each with several drive and beta ratio options, for a total cell count of 186. We show that synthesis performs better with the inclusion of more complex cells (but only if they are power efficient), we augment the synthesis library to include...
Assuming arbitrary (continuous cell sizes) we have achieved global minimization of the total transistor sizes needed to achieve a delay goal, thus minimizing dynamic power (and reducing leakage power). We then developed a feasible branch-and-bound algorithm that maps the continuous sizes to the discrete sizes available in the standard cell library. Results show that a well-designed library gives results...
We propose a methodology to determine the contents of a power efficient library: a set of sizes (drives) and beta ratios (pMOS widths divided by nMOS widths) that will enable a designer to achieve the best power versus delay tradeoff. The methodology utilizes an optimum continuous gate sizing tool. The software is not only able to produce the optimum continuous power-delay trade-off curve but also...
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