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This chapter discusses various implications of the 3D integration technology on the design methodologies, flows, and associated tools. The experiences from the advanced 2D technologies are extrapolated and combined with the incremental challenges posed by the 3D technologies, and the requirements for design ecosystem for 3D technologies are precipitated. The chapter is organized in five sections....
Efficient processing of fine-pitched Through Silicon Vias, micro-bumps and back-side re-distribution layers enable face-to-back or face-to-face integration of heterogeneous ICs using 3D stacking and/or Silicon Interposers. While these technology features are extremely compelling, they considerably stress the existing design practices and EDA tool flows typically conceived for 2D systems. With all...
A calibrated pathfinding on silicon interposer is presented for exploring the impact of interconnect geometries on signal integrity. ABCD matrix-based model and single bit method are used for the pathfinding by estimating the worst-case eye opening. Experiment-based eye-diagrams using measured S-parameters on the fabricated silicon interposer are compared with the pathfinding showing 6% max difference...
Power and substrate domains are strategically isolated or unified in heterogeneous 3D integration. In-tier probing circuitry provides accessibility to power delivery and substrate networks in a deep tier of a 3D chip stack and capability of diagnosing intra/inter tier coupling. A two-tier demonstrator was successfully tested in a 130 nm CMOS, 3D-SIC Cu TSV technology.
We present a test structure to measure the impact of 3D processing, especially through silicon vias, on FET devices. We also show proven techniques for enabling large numbers of devices to be accessed from a limited number of pads. We will show that through silicon via (TSV) proximity and FET channel length impact the device's behavior. We will show behavior can be predicted by symmetry. Through measurement,...
Three dimensional integration complements semiconductor scaling; it enables a higher integration density as well as heterogeneous technology integration. Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety...
3D Integration emerges as an attractive option to sustain Moore's law as well as to enable More-than-Moore. Design and test techniques and methodologies for 3D designs are imperative to realise 3D integration; novel architectures and design space exploration at the architectural level are also essential to leverage 3D integration technologies for performance gain. This special issue of IET Computers&Digital...
In this paper we present test structures and measurement techniques that enable extraction of significance of effects expected in 3D TSV technologies. The DAC test structure is optimized to detect Ion changes down to 0.5% due to TSV proximity, TSV orientation, thermal hotspots and wafer thinning/stacking process. The results obtained from the stand-alone MOS devices and the DAC structure clearly indicate...
In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked dies (tiers). This allows redesigning the memory tier as a configurable product to be used in multiple system designs. Previously proposed dynamic re-configurable solutions demonstrate strong dependence between read latency...
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