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FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed...
This paper reports a novel silicon microcantilever sensor with an embedded n-type metal-oxide semiconductor field-effect transistor (nMOSFET) for the detection of relative humidity (RH) based on the surface stress sensing principle. The nMOSFET has a channel along <100> crystal orientation of (100) silicon, which is parallel to the microcantilever. The RH detection is realized by coating a thin...
Traditional IC scaling is becoming increasingly difficult at the 22 nm node and beyond. Dealing with these challenges increase product development cycle time. For continued CMOS scaling, it is essential to start design explorations in new process nodes as early as possible. Such an effort requires having Predictive Technology Models, which bridge technological and design practices, in order to assess...
This paper investigates the additional iron loss generated in the laminated silicon sheets of the core or the magnetic shields of large power transformers due to the leakage flux. A verification model is well established, and an efficient analysis method is implemented and validated. Both the magnetic and electric anisotropy of the oriented silicon steel sheets are taken into account in 3-D FEM eddy...
In this study, a field-emission cathode ray tube (FE-CRT) has been fabricated using novel kind of electron emitter called carbon nano-exit (CNX) which has been developed on nickel, silicon and SUS substrate with a special plasma chemical vapor deposition (CVD) technique. Scanning electron microscopy(SEM) image indicates that the emitters have an array density of 2times108/cm2.
We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing...
Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
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