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This paper reports new accurate and scalable behavioral modeling for novel 3D field-programmable ESD protection circuits using Verilog-A, which enables post-Si on-chip and insystem ESD protection design simulation and verification. New field-programmable ESD protection devices were fabricated in CMOS-compatible processes utilizing SONOS and nano crystal dots structures. The ESD behavior models were...
This paper reports the first SONOS-based field-programmable ESD protection concept and structure. Prototype in 130nm CMOS demonstrates wide ESD triggering tuning range of ∼2V and ultra low leakage of 1.2pA. It enables post-Si on-chip/in-system ESD design programmability for complex ICs.
. A series of Si nanowires are synthesized at constant temperature of 970 ○C on Si substrate by gas condensation of pure SiO vapor without any metal catalysts, by controlling the coverage of SiOx deposits. The morphologies are characterized by scan electron microscopy (SEM) and their evolution during the growth process is observed: from isolated clusters in earlier stage to linked cluster assemblies,...
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