Search results for: Hisashi Iwamoto
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A pre-trained deep convolutional neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires high power-and-area efficiency. This paper realizes a binarized CNN which treats only binary 2-values (+1/−1) for the inputs and the weights. In this case, the multiplier is replaced with an EX-NOR circuit. To reduce both power and area, we realize...
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IEEE Journal on Emerging and Selected Topics in Circuits and Systems > 2016 > 6 > 1 > 73 - 86
This paper presents a packet classifier using multiple LUT cascades for edge-valued multi-valued decision diagrams (EVMDDs ). Since the proposed one uses both DSP blocks and on-chip memories, it can efficiently use the available FPGA resources. Thus, it can realize a parallel packet classifier on a single-chip FPGA for the next generation 400 Gb/s Internet link rate (IEEE 802.3). Since it is a...
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Packet classification has become increasingly complex and important to network equipment intended for future use. A recent trend to achieve complex packet classification is to use software-based methods, which tend to be slower than hardware-based methods. For search, this typically means using ternary content-addressable memory (TCAM) to make classification feasible. However, TCAM is not well-suited...
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For green networking, Sliced Router Architecture was proposed, which controls the power consumption of routers by adjusting the routers' performance on the basis of the volume of traffic. In this architecture, any packet losses can be eliminated, but this leads to a significant increase in processing latency in some cases, which also seriously degrades the performance of routers. In this paper, we...
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Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In particular, the occupancy of packet buffer...
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Ternary content addressable memory (TCAM) is popular LSI for use in high-throughput forwarding engines on routers. However, the unique structure applied in TCAM consume huge amounts of power, therefore it restricts the applicability to deployment for handling large lookup-table capacity in IP routers. In this paper, we propose a commodity-memory based hardware architecture for the forwarding information...
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Maintaining complete network service with the current infrastructure is an urgent task due to continuous growth in network traffic. It is expected that the energy consumption of network routers may become a global environmental problem, and therefore, research and development into power reduction is well desired. Our group proposes a unique structure embedded into routers, which consists of multiple...
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Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density requires complex memory management. As a result it, it has hardly supported large numbers...
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Dual clock scheme, where master clock (CLKM) and output clock (CLKO) are applied to a SDRAM with different phase, is proposed to achieve very fast access time without area / power penalty. A circuit technique to adjust the different phase between dual clocks is described. This scheme in conjunction with 2-bit prefetch architecture enhances operating clock frequency over 200MHz without PLL/DLL on chip...
