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In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130 nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The...
This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity...
The paper presents a new, mixed analog-digital, circuit for analog sorting signals. In comparison to other circuits of this type the proposed solution offers large versatility. The main objective is its application in Neural Gas (NG) learning algorithm used to train unsupervised neural networks (NNs). However, the circuit can also be used in nonlinear processing of analog signals. It is capable of...
The paper presents a simple current-mode conscience mechanism used in hardware implemented Winner Takes All neural networks to eliminate the problem of the, so called, dead neurons. These neurons reduce the number of data classes that can be distinguished by the NN, i.e. they decrease the efficiency of the NN. The circuit has been realized in the TSMC CMOS 0.18 μm process. At data rate of about 10...
A novel, binary-tree, asynchronous, nonlinear Min/Max filter is presented in the paper. In the proposed circuit an input signal (current in this case) is first sampled in the circular delay line, controlled by a multiphase clock (8 phases in this case). In the next stage particular samples are converted to 1-bit signals with delays proportional to the values of these samples. In the following step...
The paper presents a new CMOS implementation of the initialization mechanism for Kohonen self-organizing neural networks. A proper selection of initial values of the weights of the neurons exhibits a significant impact on the quality of the learning process. A straightforward realization of the initialization block in software is simple, but in hardware it requires providing the programming signal...
A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure...
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