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Tapered TSV interconnection has begun used in CMOS Image Senor (CIS) and currently is penetrating its application in other areas, such as MEMS devices and Si Interposer. It helps relive the technical difficulties of conformal deposition of insulation layer and conducting layer and therefore it's helpful for yield improvement and cost reduction. Besides that, it helps also relieve the stress accumulation...
In this paper, a monolithic integration structure with TSV interconnections is introduced for un-cooled infrared FPA to do easy wafer-level-package. Firstly, the challenging process for making the structure will be reviewed and identified. And then process sequence for making the TSV interconnections and RDLs and CMOS compatible surface process for IR FPA will be developed. In the end, a WLP scheme...
The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced...
This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic. In this paper,...
Polyimide (PI) was a good candidate as the sacrificial layer for its compatibility with CMOS technology. This paper first presented a new patterning method of PI film and then investigated the relationships among undercut rate, the undercut limit length and the releasing hole size in the releasing step, which was helpful and important for its popularity and its application in MEMS capacitive FPA (Focal...
This paper reports the designing/simulation and experimental investigation into the Deep RIE-based micro-fabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with...
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