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The saturation of a critical gate voltage at 2-2.4 V for SiON with thickness < 1.6 nm (EOT < 1.4 nm) extends the role of digital breakdown (BD) in prolonging progressive BD at nominal voltages. As a result, the post-BD gate leakage degradation rate, which is extrapolated from a high voltage using the conventional approach, is highly overestimated, warranting one to revise the post-BD reliability...
For the first time, a new off-state drain-bias TDDB lifetime model is proposed for DENMOS devices. With the new model, the off-state drain-bias TDDB lifetime can be well predicted from the conventional gate-bias stress without extra long term drain-bias stress. The TDDB lifetime can be decoupled to three components; the small effective stress area and large voltage drop shared by the drain-extension...
For the first time, a new drain-bias TBD lifetime model is proposed to precisely predict at various Vd, Vg and channel length for ultra thin oxide. The TBD lifetime with drain-bias can be decoupled to small voltage drop at drain-side increased TBD lifetime and hot carrier effect (HCI) degraded the TBD lifetime. The mechanism of oxide breakdown with drain-bias is also well understood as oxide traps...
This paper investigates the influence of the N-type buried layer (NBL) layout and LOCOS space on the ESD performance and trigger voltage of the lateral DMOS (LDMOS) device. Without adequate LOCOS spacing, LDMOS is vulnerable to ESD damage. If the LOCOS space is sufficiently wide, adding NBL structure can further improve LDMOS ESD performance significantly. This is because NBL can switch the current...
In this work, the "multi-step" power law TDDB model is proposed for ultra thin oxide. The nitrogen concentration effect on the voltage acceleration slope in p-FET is modeled by the boron penetration, and the voltage acceleration slope can be well explained by the "multi-step" power-law TDDB model.
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