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The proposed paper shows the half adder circuit with low power consumption preferred for arithmetic operations. Leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. In the CMOS circuits Power dissipation occurs due to increasing leakage current in deep-sub micrometer regimes which is becoming a significant contributor...
The growing market of portable electronic devices demands lesser power dissipation for longer battery life and compact system. Advancement of tech nology effectively minimizes the leakage current & power and size of cell. Leakage current in cell is the dominating factor, which is greatly affects the power consumption. Optimization of power and delay is very important issue in low voltage and low...
A novel high speed low power half adder cell is proposed in this paper. The critical path consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power consumption than the standard implementation of the half adder. In this paper a MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) technique is proposed to reduce the leakage current and leakage power also and got...
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