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In this paper, the low power and high performance full adder using 11 transistors has been proposed. The GDI (gate diffusion input) technique has been used for simultaneous generation of XOR gate. The main idea behind the designing of this 11 transistors full adder to improve the performance of 10 transistors full adder design mentioned in literature by sacrificing a transistor count. While the proposed...
The growing market of portable electronic devices demands lesser power dissipation for longer battery life and compact system. Advancement of tech nology effectively minimizes the leakage current & power and size of cell. Leakage current in cell is the dominating factor, which is greatly affects the power consumption. Optimization of power and delay is very important issue in low voltage and low...
A novel high speed low power half adder cell is proposed in this paper. The critical path consist of an AND gate and an EX-OR gate. This cell offers higher speed, lower power consumption than the standard implementation of the half adder. In this paper a MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) technique is proposed to reduce the leakage current and leakage power also and got...
SRAM Bit-Cell Sleep technique is widely used in processors to reduce SRAM leakage power. However, significance of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper evaluates the effects of design parameters like ITD, DVS and VDCMIN_RET on performance of 7T SRAM bit-cell sleep technique. Impact of Process Technology...
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