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A novel true random number generator is proposed and implemented on XC6SLX16. It consumes 44 LUTs and generates output bitrate at 125 Mbps without post-processing, or 2000 Mbps with post-processing. The underlying mechanism of chaotic dynamics in Boolean chaotic oscillator is also researched. With the utilization of the proposed entropy source, the new scheme can precede referenced designs in reliability,...
In this paper, Two control methods for single-phase phase-locked loop(PLL) have been studied and validated based on a system developed by field programmable gate array (FPGA). By using hardware description language verilog HDL, the cycle integrator, the PI regulator, the sine and cosine module of single-phase PLL control system have been set up. Software analysis and hardware simulation have been...
The design of BRAM-based FIFO in FPGA with high speed and low power consumption is presented. Meanwhile, the paper improves the design with optimized cycle latency to meet the requirements of instant and stability of state flag logic circuit design to support the high-performance FIFO. Moreover, two different types of address, B2G circuit and traveling-wave architecture accumulator are used to make...
A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2...
A uniform routing architecture is presented, which offers CLB, IOB and IP Cores an identical routing resource. At the same time, some method is adopted to optimize routing performance. With all unidirectional segmented lines and long lines with inserted tap buffers, this architecture is up to 9.8% faster compared with long lines without inserted buffers and on average 14.9% over bidirectional lines...
A flexible bit-stream level evolvable hardware (EHW) platform is proposed in order to efficiently utilize the programmable logic resources of FPGA when evolving digital circuits. This platform is based on the FuDan FPGA device. An adaptive variable-size look-up-table (LUT) array structure is proposed with the optimal Genetic Algorithm to evolvable circuits. The experiment results showed that the proposed...
A novel FuDan programmable(FDP) FPGA device architecture was presented. The new 3-LUT based logic cell could increase logic density about 11% comparing with a traditional 4-input LUT. The uniquely hierarchy programmable routing fabrics and effective switch box could optimize the routing wire segments and make it possible for different length to connect directly and efficiently. The FDP FPGA device...
With the increasing of multimedia application, the network traffic have become heavy and increased the CPU loading. The main limitations for real-time multimedia networking are memory copies and interrupts. In this paper, a proposed system which have a dual CPU architecture will accelerate real-time multimedia transfer on the networking. An FPGA prototyping - Versatile is designed and implemented...
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