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This paper presents a DC/AC compact model for double-gate (DG) tunnel field-effect transistors (TFET) which is based on a unified analytical modeling framework. The closed-form model shows a good agreement with both, TCAD simulations and measurements on test structures. A Verilog-A implementation allows for a quick performance evaluation of the DC performance of logic cells. Results of a complementary...
Since the last few years, Tunnel-FETs (TFET) have moved into the center of focus. The device has the physical property to go below the milestone of 60mV/dec slope, which cannot be achieved by standard MOSFETs. In the meantime, there exists a great diversity of TFETs. In order to accurately model this TFET variety, not only a precise potential calculation is sufficient. A similar precision is needed...
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