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As technology advances, smaller feature size enables layout precision in the lateral direction. In contrast to traditional metal–insulator–metal capacitors, metal–oxide–metal (MOM) capacitors are generally of higher density and consume less area, because they adopt a 3-D topology over several metal layers to use lateral field capacitance. To achieve little area consumption, MOM capacitors require...
The design of capacitor structures have great impact on capacitance density, parasitic capacitance, routability, and matching quality of capacitor network in a SAR ADC, which may affect power, performance, and area of the whole data converter. Most of the recent studies focused on common-centroid placement and routing optimization of the capacitor network. Only few of them investigated the structures...
Capacitor arrays are widely used in analog and mixed-signal circuit design. Most previous works solve the placement and routing problem either in a two-stage fashion or iteratively in loops, which may be more time-consuming or have less routing consideration in the placement step. To our best knowledge, this work is the first to formulate capacitor array placement and routing problem together and...
Symmetry constraints and regular structures are two major considerations for expert analog layout designers. Symmetry constraints are specified to place matched modules symmetrically with respect to some common axes to reduce unwanted electrical effects. Regular structures are commonly followed by experienced designers to enhance routability and suppress parasitics induced by extra bends of wires...
Modern circuit placement, especially analog placement, often needs to consider various constraints, such as symmetry, proximity, preplaced, variant, fixed-boundary, minimum separation, boundary, and fixed-outline constraints, for better electrical effects and higher performance. To handle these diverse constraints, topo-logical floorplan representations are pervasively used because of their higher...
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