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Ultrahigh definition television is becoming increasingly attractive and practical with the doubled compression performance delivered by High Efficiency Video Coding (H.265/HEVC). Meanwhile, implementation of real-time video codecs is challenged by not only the huge throughput and memory bandwidth requirements but also the increased complexity of new algorithms. For motion compensation (MC) that is...
A demonstration of FPGA-based 3840×2160 UHDTV (Ultra-high definition TV) H.264 video decoding and displaying system is proposed in this paper. The proposed system can decode and display 3840×2160 video by two Altera Stratix III DE3 FPGA boards, which are connected together with each other by HSTC cable. Video processing system requires high memory bandwidth. This paper locate decoder module and display...
Motion estimation and motion compensation in HEVC and similar video codecs involve huge memory traffic in storing and loading reference frames. The resulting memory power composes a significant portion of system energy consumption. This paper presents a memory power reduction framework that losslessly compresses and decompresses reference frames on-the-fly. We first present the architecture that supports...
This paper proposes a computation complexity reduction algorithm for region-of-interest (ROI) based H.264 encoding. Smaller partition is preferred in both higher visual quality and ROI situation so that inter mode selection is applied according to the ROI based quality difference. An unequal coding efficiency degradation scheme is proposed according to the unequal bits allocation in ROI based video...
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