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FinFETs are new structures for scaling the devices at sub-nanometer regime to continue the Moore's law. To increase the performance of FinFETs, a dual metal gate with underlap concepts has been introduced. Moreover, its performance can be enhanced by spacers. The dual metal gate comprises of two different workfunction materials (Molybdenum and Tungsten) for double gate (DG) and triple gate (TG) FinFET...
On scaling the conventional MOSFET in sub-micrometer regime, the short channel effects (SCEs) deteriorates the device performance. Owing to a new device structure (FinFET) has been introduced. This paper presents the effect of variation in different parameters of FinFET such as structure, dimension, doping and oxide material used for various electrical characteristics (on-state current (Ion), Subthreshold...
In this paper we propose a novel bottom spacer Bulk FinFET structure for logic applications suitable for system-on-chip (SOC) requirements. It solves the problem associated with the width quantization effect with optimized spacer height. Using well-calibrated device models and simulations, we have shown that Bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized...
A new circuit technique is proposed in this paper for reducing both the subthreshold and gate oxide leakage power in the domino logic circuits. Three high-Vt sleep transistors are added to the standard domino logic circuit to place the circuit into low leakage state. Proposed circuit is evaluated at 110°C and 25°C. At 110°C, proposed circuit reduces leakage power consumption by up to 63%, and at 25°C,...
In this paper, we analyze and compare different keeper design topologies for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity and reducing the subthreshold leakage energy of domino logic circuits. This work briefly surveys domino keeper techniques for high fan-in domino circuits. We compared the power, delay, process tracking and VDD tracking of different...
A new circuit technique is proposed in this literature to simultaneously reduce subthreshold leakage as well as gate-oxide leakage in ultra-deep submicron technology, as gate leakage is dominant for ultra thin gate insulating layer (i.e. tox > 20Å). Here we are using the dual threshold voltage technique to reduce the leakage current as well as propagation delay and sleep switches to further reduce...
A circuit technique is proposed in this paper for simultaneously reducing both subthreshold and gate-oxide leakage power consumption at high and low temperatures in footed domino logic circuits. A high Vt pMOS pull-up technique with feedback control utilizing both multiple-Vt and multiple Tox is added between the footer node and dynamic node to place footed domino logic circuit into a low leakage...
In CMOS circuits, scaling of threshold voltage results in increase of sub-threshold leakage current. According to the International Roadmap of Semiconductor (ITRS), leakage is projected to grow exponentially during the next decade. LECTOR is a technique for designing CMOS gates in order to reduce the leakage current without affecting the dynamic power dissipation. This paper presents the analysis...
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