Search results for: Mohab Anis

Items from 1 to 20 out of 47 results

article

Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction

Ayman Hamouda, Mohab Anis, Karim S. Karim

IEEE Transactions on Computer-Aided Design of Integrated Circuits and... > 2016 > 35 > 10 > 1630 - 1639

In deep submicron nodes, the final design patterning quality depends profoundly on the optical proximity correction (OPC) quality. The required pattern fidelity and CD uniformity can never be achieved without good OPC. However, OPC runtime-resource factor has been exponentially increasing every technology node reaching alarming levels, where the OPC cost in terms of resources and turn-around-time...

chapter

Hotspot detection using machine learning

Kareem Madkour, Sarah Mohamed, Dina Tantawy, Mohab Anis

2016 17th International Symposium on Quality Electronic Design (ISQED) > 405 - 409

2016 17th International Symposium on Quality Electronic Design (ISQED)

As technology nodes continue shrinking, lithography hotspot detection has become a challenging task in the design flow. In this work we present a hybrid technique using pattern matching and machine learning engines for hotspot detection. In the training phase, we propose sampling techniques to correct for the hotspot/non-hotspot imbalance to improve the accuracy of the trained Support Vector Machine...

chapter

8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design

Amr M. S. Tosson, Adam Neale, Mohab Anis, Lan Wei

2016 International Great Lakes Symposium on VLSI (GLSVLSI) > 239 - 244

2016 International Great Lakes Symposium on VLSI (GLSVLSI)

With continuous and aggressive technology scaling, suppressing the stand-by power is among the top priorities for SRAM design. Switching off the less-frequently accessed blocks is an efficient way to reduce the stand-by power, provided that the information stored in these blocks can be restored. Non-volatile memories (NVMs) are integrated into SRAM cells to perform the required store and restore functions...

chapter

RRAM refresh circuit: A proposed solution to resolve the soft-error failures for HfO₂/Hf 1T1R RRAM memory cell

Amr M. S. Tosson, Mohab Anis, Lan Wei

2016 International Great Lakes Symposium on VLSI (GLSVLSI) > 227 - 232

2016 International Great Lakes Symposium on VLSI (GLSVLSI)

RRAM-based memory is a promising emerging technology for both on-chip and stand-alone non-volatile data storage in advanced technologies. In addition to its small dimensions, the RRAM device has many technological advantages including its low-programming voltages, high speed, low power, CMOS-compatible fabrication process, and potentially monolithic 3D integration. However, one of the critical challenges...

article

Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Minoo Mirsaeedi, Andres J. Torres, Mohab Anis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2014 > 22 > 5 > 1170 - 1174

Multiple patterning lithography is the most likely manufacturing process for sub-32 nm technology nodes. Among different multiple patterning methods, self-aligned patterning has attracted much interest due to its robustness against overlay errors. However, self-aligned patterning compliance is subject to the litho-friendliness of the applied decomposition method. This brief establishes self-aligned...

chapter

Negative capacitance circuits for process variations compensation and timing yield improvement

Hassan Mostafa, Mohab Anis, Mohamed Elmasry

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS) > 277 - 280

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

The continued demand for higher performance in modern microprocessors places strict timing constraints on the high performance modules such as dynamic circuits and register files. In addition, the increased process variations in scaled technologies results in delay variations around its nominal value. This delay variability results in violating the timing constraints, and correspondingly, causes a...

chapter

Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design

Amr Tosson, Siddharth Garg, Mohab Anis

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC) > 368 - 373

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)

Better than worst-case (BWC) design is an design emerging paradigm in which the conservative frequency guard-bands used in conventional designs are removed at the expense of introducing a a non-zero (but small) error probability. A fundamental challenge in the design of better-than-worst-case circuits is to devise scalable and accurate techniques for error-probability estimation — in this paper we...

chapter

Layout regularity metric as a fast indicator of high variability circuits

Esraa Swillam, Kareem Madkour, Mohab Anis

2013 IEEE International SOC Conference > 43 - 48

2013 IEEE 26th International SoC Conference (SOCC)

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Layout regularity is one of the trending techniques suggested by design for manufacturability (DFM) to mitigate process variations effect. However, there is no study relating either lithography or electrical variations to layout regularity. In this paper, a...

article

Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow

Haitham Eissa, Rami Fathy Salem, Ahmed Arafa, Sherif Hany, more

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2013 > 21 > 5 > 807 - 820

As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early DFM efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been...

article

Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits

Hassan Mostafa, Mohab Anis, Mohamed Elmasry

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2013 > 21 > 1 > 92 - 101

SRAM has become the dominant block in modern ICs and constitutes more than 50% of the die area. The increase of process variations with continued CMOS technology scaling is considered one of the major challenges for SRAM designers. This process variations increase causes the SRAM cells to functionally fail and reduces the chip functional yield considering the static noise margin stability failures...

article

Timing yield analysis considering process-induced temperature and supply voltage variations

Kian Haghdad, Mohab Anis

Microelectronics Journal > 2012 > 43 > 12 > 956-961

Process variations cause fluctuations in the threshold voltage of integrated circuits (ICs). The variations, in turn, lead to uncertainties in the leakage current, drawn off the power grid that the underlying circuit is connected to. Because of the interdependency between the leakage power and temperature, process variations impose statistical behavior on the nodes’ supply voltage and also on the...

article

Power grid analysis and verification considering temperature variations

Kian Haghdad, Javid Jaffari, Mohab Anis

Microelectronics Journal > 2012 > 43 > 3 > 189-197

Process variations significantly impact leakage power, a pivotal parameter in designing a power grid. Because of the strong relationship between temperature and leakage power, the variations also impose statistical behavior on the operating temperature. In addition, the metal resistivity of a power grid increases with temperature. Therefore, ignoring the interdependency between leakage and temperature...

article

On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)

Hassan Mostafa, Mohab Anis, Mohamed Elmasry

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2012 > 20 > 4 > 770 - 774

An analog adaptive body bias (A-ABB) circuit is proposed in this paper. The A-ABB is used to compensate for die-to-die (D2D) and within-die (WID) parameter variations and accordingly, improves the circuit yield regarding the speed, the dynamic power, and the leakage power. The A-ABB consists of threshold voltage estimation circuits and analog control of the body bias performed by on-chip amplifier...

article

Power Yield Analysis Under Process and Temperature Variations

Kian Haghdad, Mohab Anis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2012 > 20 > 10 > 1794 - 1803

In this paper, a method is proposed to accurately estimate the power yield, considering process-induced temperature and supply voltage variations. Process variations impose statistical behavior on the temperature and leakage current. This, in turn, impacts the $IR$ drops due to the variations in the current, drawn off the power grid. By considering the process-induced statistical profile of the temperature...

chapter

AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield

Ayman Yehia Hamouda, Mohab Anis, Karim S. Karim

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) > 1603 - 1608

2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)

In this paper, we present a novel methodology for identifying lithography hot-spots and automatically transforming them into the lithography-friendly design space. This fast model-based technique is applied at the mask tape-out stage by slightly shifting and resizing the designs. It implicitly does a similar functionality as that of the Process Window OPC (PWOPC) but more efficiently. Being a relatively...

article

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

Hassan Mostafa, Mohab Anis, Mohamed Elmasry

IEEE Transactions on Semiconductor Manufacturing > 2012 > 25 > 3 > 460 - 467

Reliability and variability have become big design challenges facing submicrometer high-speed applications and microprocessors designers. A low area overhead adaptive body bias (ABB) circuit is proposed in this paper to compensate for negative-bias temperature instability (NBTI) aging and process variations to improve the system reliability and yield. The proposed ABB circuit consists of a threshold...

chapter

Power gating of VLSI circuits using MEMS switches in low power applications

Hosam Shobak, Mohamed Ghoneim, Nawal El Boghdady, Sarah Halawa, more

ICM 2011 Proceeding > 1 - 5

2011 23rd International Conference on Microelectronics (ICM)

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS...

chapter

An electrical-aware parametric DFM solution for analog circuits

Rami Fathy, Ahmed Arafa, Sherif Hany, Abdelrahman ElMously, more

2011 IEEE 6th International Design and Test Workshop (IDT) > 68 - 73

2011 IEEE 6th International Design and Test Workshop (IDT)

Today, many of the approaches that are commonly referred to as physical DFM techniques only address catastrophic defects and systematic process variations. These techniques include spreading wires, doubling vias, identification of critical areas in the circuit that are especially susceptible to defects, and identification of proximity effects caused by the lithography process. However, physical DFM...

chapter

A comparative analysis between FinFET Semi-Dynamic Flip-Flop topologies under process variations

Mohamed Rabie, Ahmed Bahgat, Khaled Ramadan, Hosam Shobak, more

2011 International Conference on Energy Aware Computing > 1 - 6

2011 International Conference on Energy Aware Computing (ICEAC 2011)

Semi-Dynamic Flip-Flops are widely used in state-of-art microprocessors. Moreover, scaling down traditional CMOS technology faces major challenges which rises the need for new devices for replacement. FinFET technology is a potential replacement due to similarity in both fabrication process and theory of operation to current CMOS technology. Hence, this paper presents the study of Semi Dynamic Flip...

article

A statistical yield optimization framework for interconnect in double patterning lithography

Minoo Mirsaeedi, Mohab Anis

Microelectronics Journal > 2011 > 42 > 11 > 1231-1238

In double patterning lithography, within-layer overlay error results in critical dimensions variability. Overlay error has been considered as a systematic source of variation; however, it is segueing into a random error for technology nodes smaller than 45-nm. Therefore, statistical design techniques should be applied to estimate and optimize the yield loss due to overlay error. In this paper, we...

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PROCESS VARIATIONS (12)
INTEGRATED CIRCUIT MODELING (8)
LOGIC GATES (8)
THRESHOLD VOLTAGE (7)
CMOS INTEGRATED CIRCUITS (6)
TRANSISTORS (6)
DELAY (5)
LITHOGRAPHY (5)
MONTE CARLO METHODS (5)
CAPACITANCE (4)
CMOS TECHNOLOGY (4)
DESIGN FOR MANUFACTURABILITY (4)
MOSFETS (4)
OPTIMIZATION (4)
POWER GRID (4)
POWER GRIDS (4)
SENSORS (4)
VOLTAGE DROP (4)
DEEP SUBMICROMETER (3)
DESIGN AUTOMATION (3)
DFM (3)
FIELD PROGRAMMABLE GATE ARRAYS (3)
NEGATIVE CAPACITANCE CIRCUIT (3)
PARAMETRIC YIELD (3)
RANDOM ACCESS MEMORY (3)
RELIABILITY (3)
STATISTICAL ANALYSIS (3)
TECHNOLOGY SCALING (3)
THERMAL ANALYSIS (3)
YIELD ESTIMATION (3)
YIELD OPTIMIZATION (3)
ADAPTIVE BODY BIAS (2)
ADAPTIVE BODY BIAS (ABB) (2)
ADAPTIVE OPTICS (2)
AGING (2)
ANALOG CIRCUITS (2)
ANALOGUE CIRCUITS (2)
ANALYTICAL MODELS (2)
COMPARATORS (CIRCUITS) (2)
COMPUTATIONAL MODELING (2)
COMPUTER ARCHITECTURE (2)
COMPUTER-AIDED DESIGN (CAD) (2)
CORRELATION (2)
DEEP SUB-MICRON (2)
DELAY ESTIMATION (2)
DESIGN (2)
DIGITAL CIRCUITS (2)
DOMINO LOGIC CIRCUITS (2)
DOUBLE PATTERNING LITHOGRAPHY (2)
ENGINES (2)
FIELD-PROGRAMMABLE GATE ARRAY (FPGA) (2)
INTEGRATED CIRCUIT DESIGN (2)
LAYOUT (2)
LEAKAGE CURRENT (2)
LEAKAGE CURRENTS (2)
LITHOGRAPHY FRIENDLY DESIGN (2)
LOGIC CAD (2)
LOW POWER DESIGN (2)
OPTICAL IMAGING (2)
OVERLAY CONTROL (2)
POWER SUPPLIES (2)
REGISTER FILE (2)
REGISTERS (2)
SEMICONDUCTOR DEVICE MODELING (2)
SIGNAL GENERATORS (2)
SOFT ERRORS (2)
SRAM CELLS (2)
TILES (2)
TIMING YIELD (2)
TIMING YIELD IMPROVEMENT (2)
VERY LARGE SCALE INTEGRATION (2)
VOLTAGE (2)
VOLTAGE VARIATIONS (2)
WITHIN-DIE (WID) VARIATIONS (2)
64-BIT ADDER (1)
64-BIT COMPARATOR (1)
AC PARAMETERS (1)
ADDERS (1)
ADVANCED SAMPLING (1)
ADVANCED VARIANCE REDUCTION (1)
ANALOG VERY LARGE SCALE INTEGRATION (VLSI) CIRCUITS (1)
ARITHMETIC FUNCTIONS (1)
ATMOSPHERIC MODELING (1)
AUTOMATION (1)
BENCHMARK CIRCUITS (1)
BENCHMARK TESTING (1)
CAD (1)
CAPACITORS (1)
CIRCUIT DELAY (1)
CIRCUIT LEVEL SCHEMES (1)
CIRCUIT SIMULATION (1)
CIRCUIT SWITCHING (1)
CIRCUITS (1)
CLASSICAL CONTROL-VARIATE TECHNIQUE (1)
CLOSED-FORM CUMULATIVE DISTRIBUTION FUNCTION (1)
CMOS DEVICE (1)
CMOS DIGITAL INTEGRATED CIRCUITS (1)
CMOS PROCESS (1)
COMBINATORIAL OPTIMIZATION (1)
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INFONA - science communication portal

Search results for: Mohab Anis

Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction

Hotspot detection using machine learning

8T1R: A novel low-power high-speed RRAM-based non-volatile SRAM design

RRAM refresh circuit: A proposed solution to resolve the soft-error failures for HfO₂/Hf 1T1R RRAM memory cell

Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning

Negative capacitance circuits for process variations compensation and timing yield improvement

Tagged probabilistic simulation based error probability estimation for better-than-worst case circuit design

Layout regularity metric as a fast indicator of high variability circuits

Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow

Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits

Timing yield analysis considering process-induced temperature and supply voltage variations

Power grid analysis and verification considering temperature variations

On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)

Power Yield Analysis Under Process and Temperature Variations

AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield

NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

Power gating of VLSI circuits using MEMS switches in low power applications

An electrical-aware parametric DFM solution for analog circuits

A comparative analysis between FinFET Semi-Dynamic Flip-Flop topologies under process variations

A statistical yield optimization framework for interconnect in double patterning lithography

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