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This work demonstrates p-type hybrid poly-Si fin channel junctionless field-effect transistor (JL-FET) with trench structure by dry etching process. This JL-FET shows superior performance in a low drain-induced barrier lowering (<10mV/V) and high Ion/Ioff (>108) for Leff = 1μm, excellent gate control.
This work demonstrates trench junctionless poly-Si thin-film transistor (JL-FET) [1] with ultra-thin body is obtained through dry etching process. JL-FET LG = 0.6μm shows excellent performance in a low drain-induced barrier lowering (DIBL), high ION/Ioff (>108), excellent gate control and reduced sensitivity to temperature in terms of VTH and SS.
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