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In recent years, our society moves towards more and more aging society, and health care becomes one of the most important concerns. Since small-size wearable and implantable healthcare systems are required in aging society, the LSI technology becomes more important for biological information sensing. In this paper, we briefly summarize the fundamental biological sensing system, and introduce our current...
This paper introduces a generation method of Application-domain Specific Instruction-set Processors (ASIP) and shows an design example. ASIP is a processor which has some extended instructions specific to application domain. First, advantage of ASIC is explained. Then, some processor generation approaches explained, and an ASIP development environment called ASIP Meister is introduced. Finally, design...
A high performance algorithm for scheduling of tasks aims to optimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the multiprocessor systems such that the precedence constraints among the tasks are preserved. In this paper, we propose an algorithm to get the optimality of scheduling for large problem sizes and optimize the target...
Multi-processor system-on-chip (MPSoC) is an integrated circuit containing multiple cores that implements most of the functionality of a complex electronic system and some other components like FPGA/ASIC on single chip. The most crucial things in such like these systems are the performance, energy, power and area optimization. Moreover, scheduling the tasks of an application on to the processors (cores)...
Systematic architecture exploration from vast solution space is a complex problem in embedded system design. It is very difficult to explore a best architecture fast and accurately because accurate evaluation usually consumes significant amount of time for point in the solution space. In this paper, we propose fast and systematic architecture exploration method for address generation unit (AGU) based...
This paper proposes an instruction set processor which uses hierarchical block-floating-point (H-BFP) arithmetic. H-BFP has been developed to provide efficient development approach for digital signal processing system. H-BFP offers highly abstracted computation model, and leads to cost-effective implementation. However, application development based on H-BFP is still time consuming task because of...
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method...
This paper proposes a method for generating a pipeline processor from the behavior description of instructions. In the proposed method, a micro-operation description is generated by complementing the behavior description with specifications of the pipeline stages, such as the number of pipeline stages, the attributes of each stage. From the behavior description, software development tools, such as...
Many dynamic reconfigurable processors are evolving rapidly that offer fast and run-time reconfiguration. To efficiently utilize run-time reconfiguration, we must consider additional memory access cycles due to reconfiguration. In general, dynamic reconfigurable processors read input data from external memory after reconfiguration and write output data to external memory before the next reconfiguration...
SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique...
In this paper, we present our methodology for virtual prototyping at high level of abstraction, to validate the execution of real time applications on simulated H/W, using RTOS centric co-simulation in System C. The basic rationale of our methodology is to build simulation models of RTOS kernels targeting the mu-ITRON OS specification standard and use these models as centre of HW/SW co-simulation...
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