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A sub-exponent TDC performs power-efficient linear phase detection. With a cascaded chain of self-calibrated 2?? time amplifiers, TDC generates the sub-exponent-only information for the fractional time difference. The TDC, implemented in a 0.18 μm CMOS, shows a minimum resolution of 1.25 ps with a total conversion range of 2.5 ns. When used in a DPLL, the rms jitter is 5 ps at 960 MHz output.
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